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d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct7046a phase-locked-loop with lock detector for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a features low power consumption centre frequency up to 17 mhz (typ.) at v cc = 4.5 v choice of two phase comparators: exclusive-or; edge-triggered jk flip-flop; excellent vco frequency linearity vco-inhibit control for on/off keying and for low standby power consumption minimal frequency drift operation power supply voltage range: vco section 3.0 to 6.0 v digital section 2.0 to 6.0 v zero voltage offset due to op-amp buffering output capability: standard i cc category: msi general description the 74hc/hct7046 are high-speed si-gate cmos devices and are specified in compliance with jedec standard no. 7. the 74hc/hct7046 are phase-locked-loop circuits that comprise a linear voltage-controlled oscillator (vco) and two different phase comparators (pc1 and pc2) with a common signal input amplifier and a common comparator input. a lock detector is provided and this gives a high level at pin 1 (ld) when the pll is locked. the lock detector capacitor must be connected between pin 15 (c ld ) and pin 8 (gnd). the value of the c ld capacitor can be determined, using information supplied in fig.32. the input signal can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. a self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. with a passive low-pass filter, the 7046 forms a second-order loop pll. the excellent vco linearity is achieved by the use of linear op-amp techniques. vco the vco requires one external capacitor c1 (between c1 a and c1 b ) and one external resistor r1 (between r 1 and gnd) or two external resistors r1 and r2 (between r 1 and gnd, and r 2 and gnd). resistor r1 and capacitor c1 determine the frequency range of the vco. resistor r2 enables the vco to have a frequency offset if required. the high input impedance of the vco simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. in order not to load the low-pass filter, a demodulator output of the vco input voltage is provided at pin 10 (dem out ). in contrast to conventional techniques where the dem out voltage is one threshold voltage lower than the vco input voltage, here the dem out voltage equals that of the vco input. if dem out is used, a load resistor (r s ) should be connected from dem out to gnd; if unused, dem out should be left open. the vco output (vco out ) can be connected directly to the comparator input (comp in ), or connected via a frequency-divider. the vco output signal has a duty factor of 50% (maximum expected deviation 1%), if the vco input is held at a constant dc level. a low level at the inhibit input (inh) enables the vco and demodulator, while a high level turns both off to minimize standby power consumption. the only difference between the hc and hct versions is the input level specification of the inh input. this input disables the vco section. the comparators sections are identical, so that there is no difference in the sig in (pin 14) or comp in (pin 3) inputs between the hc and hct versions. phase comparators the signal input (sig in ) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard hc family input logic levels. capacitive coupling is required for signals with smaller swings. phase comparator 1 (pc1) this is an exclusive-or network. the signal and comparator input frequencies (f i ) must have a 50% duty factor to obtain the maximum locking range. the transfer characteristic of pc1, assuming ripple (f r =2f i ) is suppressed, is: where v demout is the demodulator output at pin 10; v demout =v pc1out (via low-pass filter). the phase comparator gain is: the average output voltage from pc1, fed to the vco input via the low-pass filter and seen at the demodulator output at pin 10 (v demout ), is the resultant of the phase differences of signals (sig in ) and the comparator input (comp in ) as shown in fig.6. the average of v demout is equal to 1/2 v cc when there is no signal or noise at sig in and with this input the vco oscillates at the centre frequency (f o ). typical v demout v cc p ---------- - f sigin f compin C () = k p v cc p ---------- - vr () . =
december 1990 3 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a waveforms for the pc1 loop locked at f o are shown in fig.7. the frequency capture range (2f c ) is defined as the frequency range of input signals on which the pll will lock if it was initially out-of-lock. the frequency lock range (2f l ) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. the capture range is smaller or equal to the lock range. with pc1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. this configuration retains lock even with very noisy input signals. typical behaviour of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the vco centre frequency. phase comparator 2 (pc2) this is a positive edge-triggered phase and frequency detector. when the pll is using this comparator, the loop is controlled by positive signal transitions and the duty factors of sig in and comp in are not important. pc2 comprises two d-type flip-flops, control-gating and a 3-state output stage. the circuit functions as an up-down counter (fig.5) where sig in causes an up-count and comp in a down-count. the transfer function of pc2, assuming ripple (f r =f i ) is suppressed, is: where v demout is the demodulator output at pin 10; v demout =v pc2out (via low-pass filter). v demout v cc 4 p ---------- - f sigin f compin C () = the phase comparator gain is: v demout is the resultant of the initial phase differences of sig in and comp in as shown in fig.8. typical waveforms for the pc2 loop locked at f o are shown in fig.9. when the frequencies of sig in and comp in are equal but the phase of sig in leads that of comp in , the p-type output driver at pc2 out is held on for a time corresponding to the phase difference ( f demout ). when the phase of sig in lags that of comp in , the n-type driver is held on. when the frequency of sig in is higher than that of comp in , the p-type output driver is held on for most of the input signal cycle time, and for the remainder of the cycle both n and p- type drivers are off (3-state). if the sig in frequency is lower than the comp in frequency, then it is the n-type driver that is held on for most of the cycle. subsequently, the voltage at the capacitor (c2) of the low-pass filter connected to pc2 out varies until the signal and comparator inputs are equal in both phase and frequency. at this stable point the voltage on c2 remains constant as the pc2 output is in 3-state and the vco input at pin 9 is a high impedance. thus, for pc2, no phase difference exists between sig in and comp in over the full frequency range of the vco. moreover, the power dissipation due to the low-pass filter is reduced because both p and n-type drivers are off for most of the signal input cycle. it should be noted that the pll lock range for this type of phase comparator is equal to the capture range and is independent of k p v cc 4 p ---------- - vr () . = the low-pass filter. with no signal present at sig in the vco adjusts, via pc2, to its lowest frequency. applications fm modulation and demodulation frequency synthesis and multiplication frequency discrimination tone decoding data synchronization and conditioning voltage-to-frequency conversion motor-speed control
december 1990 4 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a quick reference data gnd = 0 v; t amb =25 c; notes 1. applies to the phase comparator section only (vco disabled). for power dissipation of vco and demodulator sections see figs 20, 21 and 22. 2. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i +? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct f o vco centre frequency c1 = 40 pf; r1 = 3 k w ; v cc = 5 v 19 19 mhz c i input capacitance (pin 5) 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 24 24 pf
december 1990 5 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a pin description pin no. symbol name and function 1 ld lock detector output (active high) 2 pc1 out phase comparator 1 output 3 comp in comparator input 4 vco out vco output 5 inh inhibit input 6c1 a capacitor c1 connection a 7c1 b capacitor c1 connection b 8 gnd ground (0 v) 9 vco in vco input 10 dem out demodulator output 11 r 1 resistor r1 connection 12 r 2 resistor r2 connection 13 pc2 out phase comparator 2 output 14 sig in signal input 15 c ld lock detector capacitor input 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 6 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.4 functional diagram. mga847 phase comparator 2 lock detector pc2 out ld 13 1 identical to 4046a c ld c cld 15 7046a phase comparator 2 pc2 out 13 phase comparator 3 pc3 out 15 phase comparator 1 pc1 out 2 pcp out 1 sig in comp in v co out c1 a c1 b dem out inh vco in r 2 r 1 r2 12 11 314 4 7 6 5109 (a) (b) c1 4046a vco r s r1 r4 r3 c2
december 1990 7 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.5 logic diagram. fig.6 phase comparator 1: average output voltage versus input phase difference: v demout v pc1out v cc p ---------- - f sigin f compin C () == f demout f sigin f compin C = fig.7 typical waveforms for pll using phase comparator 1, loop locked at f o .
december 1990 8 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.8 phase comparator 2: average output voltage versus input phase difference: v demout v pc2out = v cc 4 p ---------- - f sigin f compin C () = f demout f sigin f compin C () B . = fig.9 typical waveforms for pll using phase comparator 2, loop locked at f o.
december 1990 9 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a recommended operating conditions for 74hc/hct ratings limiting values in accordance with the absolute maximum system (iec 134) voltages are referenced to gnd (ground = 0 v) symbol parameter 74hc 74hct unit conditions min. typ. max. min. typ. max. v cc dc supply voltage 3.0 5.0 6.0 4.5 5.0 5.5 v v cc dc supply voltage if vco section is not used 2.0 5.0 6.0 4.5 5.0 5.5 v v i dc input voltage range 0 v cc 0v cc v v o dc output voltage range 0 v cc 0v cc v t amb operating ambient temperature range - 40 + 85 - 40 + 85 c see dc and ac character- istics t amb operating ambient temperature range - 40 + 125 - 40 + 125 c t r , t f input rise and fall times (pin 5) 6.0 1000 500 400 6.0 500 ns v cc = 2.0 v v cc = 4.5 v v cc = 6.0 v symbol parameter min. max. unit conditions v cc dc supply voltage - 0.5 + 7v i ik dc input diode current 20 ma for v i <- 0.5 v or v i > v cc + 0.5 v i ok dc output diode current 20 ma for v o <- 0.5 v or v o > v cc + 0.5 v i o dc output source or sink current 25 ma for - 0.5 v < v o < v cc + 0.5 v i cc ; i gnd dc v cc or gnd current 50 ma t stg storage temperature range - 65 + 150 c p tot power dissipation per package plastic dil 750 mw for temperature range: - 40 to +125 c 74hc/hct above + 70 c: derate linearly with 12 mw/k plastic mini-pack (so) 500 mw above + 70 c: derate linearly with 8 mw/k
december 1990 10 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a dc characteristics for 74hc quiescent supply current voltages are referenced to gnd (ground = 0 v) symbol parameter t amb ( c) unit test conditions 74hc v cc (v) other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. i cc quiescent supply current (vco disabled) 8.0 80.0 160.0 m a 6.0 pins 3, 5, and 14 at v cc ; pin 9 at gnd; i i at pins 3 and 14 to be excluded
december 1990 11 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a phase comparator section voltages are referenced to gnd (ground = 0 v) symbol parameter t amb ( c) unit test conditions 74hc v cc (v) v i other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. v ih dc coupled high level input voltage sig in , comp in 1.5 3.15 4.2 1.2 2.4 3.2 1.5 3.15 4.2 1.5 3.15 4.2 v 2.0 4.5 6.0 v il dc coupled low level input voltage sig in , comp in 0.8 2.1 2.8 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 v 2.0 4.5 6.0 v oh high level output voltage ld, pc nout 1.9 4.4 5.9 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 v 2.0 4.5 6.0 v ih or v il - i o =20 m a - i o =20 m a - i o =20 m a v oh high level output voltage ld, pc nout 3.98 5.48 4.32 5.81 3.84 5.34 3.7 5.2 v 4.5 6.0 v ih or v il - i o = 4.0 ma - i o = 5.2 ma v ol low level output voltage ld, pc nout 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v 2.0 4.5 6.0 v ih or v il i o =20 m a i o =20 m a i o =20 m a v ol low level output voltage ld, pc nout 0.15 0.16 0.26 0.26 0.33 0.33 0.4 0.4 v 4.5 6.0 v ih or v il i o = 4.0 ma i o = 5.2 ma i i input leakage current sig in , comp in 3.0 7.0 18.0 30.0 4.0 9.0 23.0 38.0 5.0 11.0 27.0 45.0 m a 2.0 3.0 4.5 6.0 v cc or gnd i oz 3-state off-state current pc2 out 0.5 5.0 10.0 m a 6.0 v ih or v il v o =v cc or gnd r i input resistance sig in , comp in 800 250 150 k w 3.0 4.5 6.0 v i at self-bias operating point; d v i = 0.5 v; see figs 10, 11 and 12
december 1990 12 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a vco section voltages are referenced to gnd (ground = 0 v) note 1. the parallel value of r1 and r2 should be more than 2.7 k w . optimum performance is achieved when r1 and/or r2 are/is > 10 k w . sym- bol parameter t amb ( c) unit test conditions 74hc v cc (v) v i other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. v ih high level input voltage inh 2.1 3.15 4.2 1.7 2.4 3.2 2.1 3.15 4.2 2.1 3.15 4.2 v 3.0 4.5 6.0 v il low level input voltage inh 1.3 2.1 2.8 0.9 1.35 1.8 0.9 1.35 1.8 0.9 1.35 1.8 v 3.0 4.5 6.0 v oh high level output voltage vco out 2.9 4.4 5.9 3.0 4.5 6.0 2.9 4.4 5.9 2.9 4.4 5.9 v 3.0 4.5 6.0 v ih or v il - i o =20 m a - i o =20 m a - i o =20 m a v oh high level output voltage vco out 3.98 5.48 4.32 5.81 3.84 5.34 3.7 5.2 v 4.5 6.0 v ih or v il - i o = 4.0 ma - i o = 5.2 ma v ol low level output voltage vco out 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v 3.0 4.5 6.0 v ih or v il i o =20 m a i o =20 m a i o =20 m a v ol low level output voltage vco out 0.15 0.16 0.26 0.26 0.33 0.33 0.4 0.4 v 4.5 6.0 v ih or v il i o = 4.0 ma i o = 5.2 ma v ol low level output voltage c1 a, c1 b (test purposes only) 0.40 0.40 0.47 0.47 0.54 0.54 v 4.5 6.0 v ih or v il i o = 4.0 ma i o = 5.2 ma i i input leakage current inh, vco in 0.1 1.0 1.0 m a 6.0 v cc or gnd r1 resistor range 3.0 3.0 3.0 300 300 300 k w 3.0 4.5 6.0 note 1 r2 resistor range 3.0 3.0 3.0 300 300 300 k w 3.0 4.5 6.0 note 1 c1 capacitor range 40 40 40 no limit pf 3.0 4.5 6.0 v vcoin operating voltage range at vco in 1.1 1.1 1.1 1.9 3.4 4.9 v 3.0 4.5 6.0 over the range speci?ed for r1; for linearity see figs 18 and 19.
december 1990 13 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a demodulator section voltages are referenced to gnd (ground = 0 v) symbol parameter t amb ( c) unit test conditions 74hc v cc (v) other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. r s resistor range 50 50 50 300 300 300 k w 3.0 4.5 6.0 at r s > 300 k w the leakage current can in?uence v demout v off offset voltage vco in to v demout 30 20 10 mv 3.0 4.5 6.0 v i =v vcoin = 1/2 v cc ; values taken over r s range; see fig.13 r d dynamic output resistance at dem out 25 25 25 w 3.0 4.5 6.0 v demout = 1/2 v cc
december 1990 14 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a ac characteristics for 74hc phase comparator section gnd = 0 v; t r =t f = 6 ns; c l = 50 pf vco section gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay sig in , comp in to pc1 out 58 21 17 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 fig.14 t pzh / t pzl 3-state output enable time sig in , comp in to pc2 out 74 27 22 280 56 48 350 70 60 420 84 71 ns 2.0 4.5 6.0 fig.15 t phz / t plz 3-state output disable time sig in , comp in to pc2 out 96 35 28 325 65 55 405 81 69 490 98 83 ns 2.0 4.5 6.0 fig.15 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.14 v i(p-p) ac coupled input sensitivity (peak-to-peak value) at sig in or comp in 9 11 15 33 mv 2.0 3.0 4.5 6.0 f i = 1 mhz sym- bol parameter t amb ( c) unit test conditions 74hc v cc (v) other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. typ. max. min. max. d f/t frequency stability with temperature change 0.20 0.15 0.14 %/k 3.0 4.5 6.0 v i =v vcoin =1/2 v cc ; r1 = 100 k w ; r2 = ; c1 = 100 pf; see fig.16 f o vco centre frequency (duty factor = 50%) 7.0 11.0 13.0 10.0 17.0 21.0 mhz 3.0 4.5 6.0 v vcoin = 1/2 v cc ; r1 = 3 k w ; r2 = ; c1 = 40 pf; see fig.17 d f vco vco frequency linearity 1.0 0.4 0.3 % 3.0 4.5 6.0 r1 = 100 k w ; r2 = ; c1 = 100 pf; see figs 18 and 19 d vco duty factor at vco out 50 50 50 % 3.0 4.5 6.0
december 1990 15 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a dc characteristics for 74hct quiescent supply current voltages are referenced to gnd (ground = 0 v) note 1. the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given above. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. i cc quiescent supply current (vco disabled) 8.0 80.0 160.0 m a 6.0 pins 3, 5 and 14 at v cc ; pin 9 at gnd; i i at pins 3 and 14 to be excluded d i cc additional quiescent supply current per input pin for unit load coef?cient is 1 (note 1) v i =v cc - 2.1 v 100 360 450 490 m a 4.5 to 5.5 pins 3 and 14 at v cc ; pin 9 at gnd; i i at pins 3 and 14 to be excluded input unit load coefficient inh 1.00
december 1990 16 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a phase comparator section voltages are referenced to gnd (ground = 0 v) sym bol parameter t amb ( c) unit test conditions 74hct v cc (v) v i other + 25 - 40 to + 85 - 40 to + 125 min. typ. max min. max. min. max. v ih dc coupled high level input voltage sig in , comp in 3.15 2.4 v 4.5 v il dc coupled low level input voltage sig in , comp in 2.1 1.35 v 4.5 v oh high level output voltage ld, pc nout 4.4 4.5 4.4 4.4 v 4.5 v ih or v il - i o =20 m a v oh high level output voltage ld, pc nout 3.98 4.32 3.84 3.7 v 4.5 v ih or v il - i o = 4.0 ma v ol low level output voltage ld, pc nout 0 0.1 0.1 0.1 v 4.5 v ih or v il i o =20 m a v ol low level output voltage ld, pc nout 0.15 0.26 0.33 0.4 v 4.5 v ih or v il i o = 4.0 ma i i input leakage current sig in , comp in 30 38 45 m a 5.5 v cc or gnd i oz 3-state off-state current pc2 out 0.5 5.0 10.0 m a 5.5 v ih or v il v o =v cc or gnd r i input resistance sig in , comp in 250 k w 4.5 v i at self-bias operating point; d v i = 0.5 v; see figs 10, 11 and 12
december 1990 17 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a dc characteristics for 74hct vco section voltages are referenced to gnd (ground = 0 v) note 1. the parallel value of r1 and r2 should be more than 2.7 k w . optimum performance is achieved when r1 and/or r2 are/is > 10 k w . symbol parameter t amb ( c) unit test conditions 74hct v cc (v) v i other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. v ih high level input voltage inh 2.0 1.6 2.0 2.0 v 4.5 to 5.5 v il low level input voltage inh 1.2 0.8 0.8 0.8 v 4.5 to 5.5 v oh high level output voltage vco out 4.4 4.5 4.4 4.4 v 4.5 v ih or v il - i o =20 m a v oh high level output voltage vco out 3.98 4.32 3.84 3.7 v 4.5 v ih or v il - i o = 4.0 ma v ol low level output voltage vco out 0 0.1 0.1 0.1 v 4.5 v ih or v il i o =20 m a v ol low level output voltage vco out 0.15 0.26 0.33 0.4 v 4.5 v ih or v il i o = 4.0 ma v ol low level output voltage c1 a , c1 b (test purposes only) 0.40 0.47 0.54 v 4.5 v ih or v il i o = 4.0 ma i i input leakage current inh, vco in 0.1 1.0 1.0 m a 5.5 v cc or gnd r1 resistor range 3.0 300 k w 4.5 note 1 r2 resistor range 3.0 300 k w 4.5 note 1 c1 capacitor range 40 no limit pf 4.5 v vcoin operating voltage range at vco in 1.1 3.4 v 4.5 over the range speci?ed for r1; for linearity see figs 18 and 19.
december 1990 18 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a demodulator section voltages are referenced to gnd (ground = 0 v) ac characteristics for 74hct phase comparator section gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. r s resistor range 50 300 k w 4.5 at r s > 300 k w the leakage current can in?uence v demout v off offset voltage vco in to v demout 20 mv 4.5 v i =v vcoin = 1/2 v cc ; values taken over r s range; see fig.13 r d dynamic output resistance at dem out 25 w 4.5 v demout = 1/2 v cc symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay sig in , comp in to pc1 out 21 40 50 60 ns 4.5 fig.14 t pzh / t pzl 3-state output enable time sig in , comp in to pc2 out 27 56 70 84 ns 4.5 fig.15 t phz / t plz 3-state output disable time sig in , comp in to pc2 out 35 65 81 98 ns 4.5 fig.15 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.14 v i(p-p) ac coupled input sensitivity (peak-to-peak value) at sig in or comp in 15 mv 4.5 f i = 1 mhz
december 1990 19 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a vco section gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other + 25 - 40 to + 85 - 40 to + 125 min. typ. max. typ. max. min. max. d f/t frequency stability with temperature change 0.15 %/k 4.5 v i =v coin within recommended range; r1 = 100 k w ; r2 = ; c1 = 100 pf; see fig.16b f o vco centre frequency (duty factor = 50%) 11.0 17.0 mhz 4.5 v vcoin = 1/2 v cc ; r1 = 3 k w ; r2 = ; c1 = 40 pf; see fig.17 d f vco vco frequency linearity 0.4 % 4.5 r1 = 100 k w ; r2 = ; c1 = 100 pf; see figs 18 and 19 d vco duty factor at vco out 50 % 4.5
december 1990 20 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a figure references for dc characteristics fig.10 typical input resistance curve at sig in , comp in . fig.11 input resistance at sig in , comp in with d v i = 0.5 v at self-bias point. fig.12 input current at sig in , comp in with d v i = 0.5 v at self-bias point. fig.13 offset voltage at demodulator output as a function of vco in and r s . ____ r s = 50 k w - - - - r s = 300 k w
december 1990 21 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a ac waveforms fig.14 waveforms showing input (sig in , comp in ) to output (pc1 out ) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . fig.15 waveforms showing the 3-state enable and disable times for pc2 out . (1) hc : v m = 50%; v i = gnd to v cc .
december 1990 22 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.16 frequency stability of the vco as a function of ambient temperature with supply voltage as a parameter. ?? without offset (r2 = ): (a) r1 = 3 k w ; (b) r1 = 10 k w ; (c) r1 = 300 k w . - - - - with offset (r1 = ): (a) r2 = 3 k w ; (b) r2 = 10 k w ; (c) r2 = 300 k w . in (b), the frequency stability for r1 = r2 = 10 k w at 5 v is also given (curve a). this curve is set by the total vco bias current, and is not simply the addition of the two 10 k w stability curves. c1 = 100 pf; v vco in = 0.5 v cc . handbook, halfpage msb710 t amb ( o c) 0 150 100 50 0 - 50 - 25 - 20 - 15 - 10 - 5 5 10 15 20 25 d f (%) 5 v 6 v 3 v 4.5 v 5 v 6 v v = cc 3 v (a) handbook, halfpage msb711 t ( c) amb 0 f (%) o 150 100 50 0 50 25 20 15 10 5 5 10 15 20 25 d 5 v 6 v 3 v 5 v 6 v v = cc 3 v (b) a handbook, halfpage msb712 t ( c) amb 0 f (%) o 150 100 50 0 50 25 20 15 10 5 5 10 15 20 25 d 5 v 6 v (c) v = cc 3 v 3 v 6 v 5 v
december 1990 23 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a ac waveforms fig.16 continued. to obtain optimum temperature stability, c 1 must be a small as possible, but larger than 100 pf.
december 1990 24 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.17 graphs showing vco frequency (f vco ) as a function of the vco input voltage (v vcoin ).
december 1990 25 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.18 definition of vco frequency linearity: d v = 0.5 v over the v cc range: for vco linearity f 0 f 1 f 2 + 2 -------------- - = linearity f 0 f 0 C f 0 ---------------- 100 % = fig.19 frequency linearity as a function of r1, c1 and v cc : r2 = and d v = 0.5 v.
december 1990 26 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.20 power dissipation versus the value of r1: c l = 50 pf; r2 = ; v vcoin = 1/2 v cc ; t amb =25 c. ____ c1 = 40 pf - - - - c1 = 1 m f fig.21 power dissipation versus the value of r2: c l = 50 pf; r1 = ; v vcoin = gnd = 0 v; t amb =25 c. ____ c1 = 40 pf - - - - c1 = 1 m f fig.22 typical dc power dissipation of demodulator section as a function of r s : r1 = r2 = ; t amb =25 c; v vcoin = 1/2 v cc .
december 1990 27 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a application information this information is a guide for the approximation of values of external components to be used with the 74hc/hct7046 in a phase-lock-loop system. references should be made to figs 27, 28 and 29 as indicated in the table. values of the selected components should be within the following ranges : r1 between 3 k w and 300 k w; r2 between 3 k w and 300 k w; r1 + r2 parallel value > 2.7 k w ; c1 greater than 40 pf. subject phase comparator design considerations vco frequency characteristic vco frequency without extra offset pc1, pc2 with r2 = and r1 within the range 3 k w< r1 < 300 k w , the characteristics of the vco operation will be as shown in fig. 23. (due to r1, c1 time constant a small offset remains when r2 = .) fig. 23 frequency characteristic of vco operating without offset: f o = centre frequency; 2f l = frequency lock range. selection of r1 and c1 pc1 given f o , determine the values of r1 and c1 using fig.27. pc2 given f max and f o , determine the values of r1 and c1 using fig.27, use fig.29 to obtain 2f l and then use this to calculate f min.
december 1990 28 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a vco frequency characteristic vco frequency with extra offset pc1, pc2 with r1 and r2 within the ranges 3 k w< r1 < 300 k w, 3 k w< r2 < 300 k w , the characteristics of the vco operation will be as shown in fig. 24. fig. 24 frequency characteristic of vco operating with offset: f o = centre frequency; 2f l = frequency lock range. selection of r1, r2 and c1 pc1, pc2 given f 0 and f l , determine the value of product r1c1 by using fig.29. calculate f off from the equation f off =f o - 1.6f l . obtain the values of c1 and r2 by using fig.28. calculate the value of r1 from the value of c1 and the product r1c1. subject phase comparator design considerations
december 1990 29 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a pll conditions with no signal at the sig in input pc1 vco adjusts to f o with f demout =90 and v vcoin = 1/2 v cc (see fig.6). pc2 vco adjusts to f o with f demout = - 360 and v vcoin = min. (see fig.8). pll frequency capture range pc1, pc2 loop ?lter component selection (a) t = r3 x c2 (b) amplitude characteristic (c) pole-zero diagram fig. 25 simple loop ?lter for pll without offset; r3 3 500 w . (a) t 1 = r3 x c2; (b) amplitude characteristic (c) pole-zero diagram t 2 = r4 x c2; t 3 = (r3 + r4) x c2 fig. 26 simple loop ?lter for pll with offset; r3 + r4 3 500 w . pll locks on harmonics at centre frequency pc1 yes pc2 no noise rejection at signal input pc1 high pc2 low ac ripple content when pll is locked pc1 f r =2f i , large ripple content at f demout =90 pc2 f r =f i , small ripple content at f demout =0 subject phase comparator design considerations
december 1990 30 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.27 typical value of vco centre frequency (f o ) as a function of c1: r2 = ; v vcoin = 1/2 v cc ; inh = gnd; t amb =25 c. (1) to obtain optimum vco performance, c1 must be as small as possible but larger than 100 pf. (2) interpolation for various values of r1 can be easily calculated because a constant r1c1 product will produce almost the same vco output frequency.
december 1990 31 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a application information fig.28 typical value of frequency offset as a function of c1: r1 = ; v vcoin = 1/2 v cc ; inh = gnd; t amb =25 c. (1) to obtain optimum vco performance, c1 must be as small as possible but larger than 100 pf. (2) interpolation for various values of r2 can be easily calculated because a constant r2c2 product will produce almost the same vco output frequency.
december 1990 32 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.29 typical frequency lock range (2f l ) versus the product r1c1: v vcoin range = 0.9 to (v cc - 0.9) v; r2 = ; vco gain: k v 2f l v vcoin range ------------------------------------ - 2 p (r/s/v). =
december 1990 33 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a application information lock-detection circuit the built-in lock-detection circuit will only work when used in conjunction with the phase comparator pc2. the lock-indication is derived from the phase error between sig in and comp in . the pc2 has a typical phase error of zero degrees over the entire vco operating range. however, to remain in-lock the circuit requires some small adjustments. the variation is dependent on the loop parameters and back-lash time (typically 5 ns). depending on the application, the phase error can be defined as the limit, a phase error of greater magnitude would be considered out-of-lock. an example of an in-lock detection circuit using the 7046a is shown in fig.30. if the pll is in-lock, only very small pulses will come from the up or down connections of pc2. these pulses are filtered out by a rc network. a schmitt trigger produces a steady state level, a high level indicates an in-lock condition and a pulsed output indicates an out-of-lock condition as shown in fig.31. fig.30 an example of an in-lock detection circuit using the 7046a. see fig.31 for input waveform. fig.31 waveforms showing the lock detection process; (a) in-lock; (b) out-of-lock. (a) (b)
december 1990 34 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a fig.32 c ld capacitor value versus typical t ld . c ld = capacitor connected to pin 15 (includes the parasitic input capacitance of the ic, approximately 3.5 pf). t ld = phase difference between sig in and comp in (positive-going edges).
december 1990 35 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a the maximum permitted phase error must be defined, before t ld can be defined using the following formula: using this calculated value in fig.32, it is possible to define the value of c ld , e.g. assuming the phase error is 36 and f in = 2 mhz: and using fig.32, it can be seen that c ld is 26 pf. with the addition of one retriggerable monostable (e.g. 123, 423 or 4538) a steady state low and high indication can be obtained, as shown in fig.33. t ld f max 360 ------------ 1 f in ------ . = t ld 36 360 --------- - 1 2mhz ----------------- 50 ns, = = fig.33 steady state signal for lock indication.
december 1990 36 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a pll design example the frequency synthesizer, used in the design example shown in fig.34, has the following parameters: output frequency: 2 mhz to 3 mhz frequency steps : 100 khz settling time : 1 ms overshoot : < 20% the open-loop gain is h (s) x g (s) = k p k f k o k n . where: the programmable counter ratio k n can be found as follows: the vco is set by the values of r1, r2 and c1, r2 = 10 k w (adjustable). the values can be determined using the information in the section design considerations. with f o = 2.5 mhz and f l = 500 khz this gives the following values (v cc = 5.0 v): r1 = 10 k w r2 = 10 k w c1 = 500 pf the vco gain is: the gain of the phase comparator is: the transfer gain of the filter is given by: where: k p = phase comparator gain k f = low-pass filter transfer gain k o =k v /s vco gain k n = 1/n divider ratio n min. f out f step ---------- - 2 mhz 100 khz ---------------------- 20 == = n max. f out f step ---------- - 3mhz 100 khz ---------------------- 30 == = k v 2f l 2 p 0.9 v cc 0.9 C () C ---------------------------------------------- 1mhz 3.2 ----------------- 2 p 210 6 r/s/v ? = == k p v cc 4 p ------------ 0.4 v/r. == k f 1 t 2 s + 1 t 1 t 2 + () s + ------------------------------------ - = t 1 r3c2 and t 2 r4c2. = = the characteristics equation is: 1 + h (s) g (s) = 0. this results in: the natural frequency w n is defined as follows: and the damping value z is defined as follows: the overshoot and settling time percentages are now used to determine w n . from fig.35 it can be seen that the damping ratio z = 0.8 will produce an overshoot of less than 20% and settle to within 5% at w n t = 4.5. the required settling time is 1 ms. this results in: rewriting the equation for natural frequency results in: the maximum overshoot occurs at n max .: when c2 = 470 nf, then r3 is calculated using the damping ratio equation: s 2 1k p k v k n t 2 + t 1 t 2 + () ----------------------------------------------------- s k p k v k n t 1 t 2 + () -------------------------------- 0. = ++ w n k p k v k n t 1 t 2 + () -------------------------------- B . = z 1 2 w n ---------- 1k p k v k n t 2 + t 1 t 2 + ----------------------------------------------------- . = w n 5 t -- - 5 0.001 -------------- - 510 3 r/s. == = t 1 t 2 + () k p k v k n w n 2 -------------------------------- . = t 1 t 2 + () 0.4 2 10 6 5000 2 30 --------------------------------- 0.0011 s. == r4 t 1 t 2 + () 2 w n z 1 C k p k v k n ---------------------------------------------------------------- - 790 w . == r3 t 1 c2 ------- - r4 2 k w . = C =
december 1990 37 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a note for an extensive description and application example please refer to application note ordering number 9398 649 90011. also available a computer design program for plls ordering number 9398 961 10061. since the output frequency is proportional to the vco control voltage, the pll frequency response can be observed with an oscilloscope by monitoring pin 9 of the vco. the average frequency response, as calculated by the laplace method, is found experimentally by smoothing this voltage at pin 9 with a simple rc filter, whose time constant is long compared to the phase detector sampling rate but short compared to the pll response time. fig.34 frequency synthesizer. fig.35 type 1, second order frequency step response. 012 4 1.6 1.0 0.6 0 0.8 mga959 3 1.4 1.2 0.4 0.2 5678 w n t dw (t) e dw e / w n df (t) e df e / w n - 0.6 0 0.4 1.0 0.2 - 0.4 - 0.2 0.6 0.8 = 5.0 z 0.5 0.707 1.0 = 0.3 z = 2.0 z
december 1990 38 philips semiconductors product speci?cation phase-locked-loop with lock detector 74hc/hct7046a package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.36 frequency compared to the time response.

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